Field of the Invention
The invention is directed to an electronic apparatus and more particularly, to a clock and data recovery (CDR) apparatus.
Description of Related Art
In some channel signal protocols for clock-embedded display interface circuits, a transmitting terminal segments data and forms a packet by adding a plurality of data segments (e.g., N data segments) with a header. The header may contain dummy clock data with a certain transition encoding form, such as “01”, “10”, “001”, “110”, “011”, “100”, “0011” or “1100”, such that phase information of clock signals may be embedded into a data signal. A clock and data recovery (CDR) apparatuses at a receiving terminal may extract the clock signals from the data signal according to the dummy clock data contained in the header. CDR apparatuses may generally be categorizes as a delay locked loop (DLL) type and a phase locked loop (PLL) type. In comparison of the two architectures, a conventional DLL type CDR apparatus has better capability for data jitter tolerance, but poor capability for suppressing power noise. The main reason lies on the conventional DLL type CDR apparatus having a recovered clock cycle of N, i.e., the clock signals being corrected per N segments of data. As a result, the conventional DLL type CDR apparatus may not be capable of responding to fast and intense power noise in time.